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Keynote Speakers
Keynote Speakers

 

Ming Liu,
Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), China

 

Yong Lian,
President of IEEE CAS Society

 


Meng-Fan Chang,

National Tsing Hua University, Taiwan
Professor, EE Dept., National Tsing Hua University (NTHU), Taiwan
Program Director, Microelectronics Program, Ministry of Science and Technology (MOST), Taiwan, 2018-2020
IEEE Distinguished Lecturer (DL), Circuits and System Society (CASS)

Dr. Chang is a full Professor in the Dept. of Electrical Engineering of National Tsing Hua University (NTHU), Taiwan. Dr. Change obtained considerable practical experience before joining NTHU in 2006, having spent more than 10 years working in industry.
Between 1997 and 2006, Dr. Chang worked in the development of SRAM/ROM/Flash macros/compilers at Mentor Graphics (New Jersey, US), TSMC (Taiwan), and the Intellectual Property Library Company (Taiwan). His research interests include circuit design for volatile and nonvolatile memory, 3D-Memory, nonvolatile and spintronics logics, circuit-device-interactions in non-CMOS devices, memristor circuits, computing-in-memory and neuromorphic circuits for deep learning and artificial intelligent (AI) chips.            

Since 2010, Dr. Chang has authored or co-authored more than 40+ top conference papers (including 14 ISSCC, 15 VLSI Symposia, 8 IEDM, and 5 DAC) as well as 40+ IEEE journal papers and 40+ US patents. He is an associate editor for IEEE TVLSI, and IEEE TCAD. He has been serving on technical program committees for ISSCC, IEDM (Executive committee, Chair of MT sub-committee), DAC, A-SSCC, IEEE CAS Society (Chair Elect of NG-TC), and numerous international conferences. He is a Distinguished Lecturer (DL) for IEEE Circuits and Systems Society (CASS) during 2017-2018. He is the recipient of several prestigious national-level awards in Taiwan, including the Outstanding Research Award of MOST-Taiwan, Outstanding Electrical Engineering Professor Award, Ta-You Wu Memorial Award, Academia Sinica Junior Research Investigators Award, Outstanding Chip Design Awards, and Golden Silicon Awards. He currently is the Program Director of the Microelectronics Program at the Ministry of Science and Technology (MOST) in Taiwan.

Speech Title: Next-Generation Energy-Efficient Computing for IoT and AI Chips: How to Overcome the Memory Wall
Abstract: Memory has proven a major bottleneck in the development of energy-efficient chips for IoT applications and artificial intelligence (AI). Recent memory devices not only serve as memory macros, but also enable the development of nonvolatile logics (nvLogics) and computing-in-memory (CIM) for IoT and AI chips. In this talk, we will review recent trend of IoT and AI chips. Then, we will examine some of the challenges, circuits-devices-interaction, and recent progress involved in the further development of SRAM, emerging memory (STT-MRAM, ReRAM and PCM), nvLogics and CIMs for IoT and AI chips.

 

 

Zhangming Zhu,
Xidian University, China

 

 


David Z. Pan,
The University of Texas at Austin, United States

David Z. Pan received his B.S. degree from Peking University, and his M.S. and Ph.D. degrees from University of California, Los Angeles (UCLA). From 2000 to 2003, he was a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. He has been an Assistant Professor (2003-2008), Associate Professor (2008-2013), Professor (2013-), and Engineering Foundation Endowed Professor (2014-) with the Department of Electrical and Computer Engineering, The University of Texas at Austin. His research interests include cross-layer nanometer IC design for manufacturability/reliability, new frontiers of physical design, and CAD for emerging technologies such as 3D-IC, bio, and nanophotonics. He has published over 300 refereed journal and conference papers, and is the holder of 8 U.S. Patents.  He has graduated 23 PhD students at UT Austin, who are now taking key academic and industry roles.

He has served as a Senior Associate Editor of ACM Transactions on Design Automation of Electronic Systems (TODAES) and an Associate Editor of IEEE Design & TestIEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), and IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), Science China Information Science (SCIS), Journal of Computer Science and Technology (JCST), and the IEEE CAS Society Newsletter. He has served as the IEEE CANDE Committee Chair, Program/General Chair of ISPD 2007/2008, TPC Chair of ASP-DAC 2017, Program Chair of ICCAD 2018, Tutorial Chair of DAC 2014, among others. He has served in the working group of the International Technology Roadmap for Semiconductor (ITRS). He has also served as an advisor or consultant to various companies including Cadence, Cooley LLP, Fish & Richardson, Pyxis, and Tabula.

He has received a number of awards for his research contributions and professional services, including the SRC 2013 Technical Excellence AwardDAC Top 10 Author in Fifth Decade, DAC Prolific Author Award, ASP-DAC Frequently Cited Author Award, 15 Best Paper Awards (Integration - the VLSI Journal 2018, HOST 2017, SPIE 2016, ISPD 2014, ICCAD 2013, ASPDAC 2012, ISPD 2011, IBM Research 2010 Pat Goldberg Memorial Best Paper Award in CS/EE/Math, ASPDAC 2010, DATE 2009, ICICDT 2009, SRC Techcon in 1998, 2007, 2012 and 2015) and 12 other Best Paper Award nominations, Communications of the ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), UT Austin RAISE Faculty Excellence Award (2014), and many international CAD contest awards, among others. He is a Fellow of IEEE and SPIE.